Image Convolution on FPGAs: The Implementation of a Multi-FPGA FIFO Structure

In this paper, we present an implementation of a real-time convolver, based on Field Programmable Gate Arrays (FPGA’s) to perform the convolution operations. Main characteristics of the proposed approach are the usage of external memory to implement a FIFO buffer where incoming pixels are stored and the partitioning of the convolution matrix among several FPGA’s, in order to allow data-parallel computation and to increase the size of the convolution kernel.